The present invention relates to cache control systems for fast cache memories in a microprocessor-based computer system. In particular, the invention relates to systems using first and second level caches, and to the replacement of first level cache lines with lines from the second level cache.
Many computer systems today use cache memories to improve the speed of access of more frequently used data and instructions. A small cache memory may be integrated on the microprocessor chip itself, thus greatly improving the speed of access by eliminating the need to go outside the chip and access data or instructions from an external DRAM memory. Another system uses a second level cache as well which is typically made up of SRAM memory chips outside the microprocessor. Access to the SRAM chips is much faster than access to the DRAM chips. The SRAM chips are much more expensive than the DRAM chips, however, so it is not cost effective to simply replace all the DRAM chips with SRAMs. Typically, a small first level cache is integrated on the microprocessor chip itself for the most frequently used data and instructions. A larger second level SRAM cache is used to store a larger amount of data and instructions, but less than the full memory.
During a normal data accessing routine, the microprocessor will first look in the first level cache to see if the desired data or instructions are resident there. If they are not, it will then go to the second level cache. If they are not resident in the second level cache, it will then go to the DRAM system memory.
The first level cache is a subset of the second level cache, which is a subset of the main memory. When writing to a memory location, a write to the first level cache must be copied to the second level cache and the main memory as well to maintain consistency. The writing to the second level cache will use up cycle time on the bus which will sometimes delay the processing of a next instruction while this "housekeeping" function of making the first level and second level caches consistent is being performed. In other situations, one of more lines from the second level cache may be brought into the first level cache even though they are not immediately needed by the microprocessor.
Some delays are especially significant when central processing unit designs attempt to achieve higher throughput by incorporating parallelism and pipelining. For example, an attempt to read something which is being copied from the second-level cache to the first level cache requires waiting for the copy to be completed, or accessing the second level cache a second time.